/*
 * @Description  : the 4KB DATA MEMORY FOR CPU
 * @authorName   : GuoJi
 * @github       : https://github.com/guoji-kk
 * @gitee        : https://gitee.com/guoji13663585559
 * @email        : 13663585559@163.com
 * @version      : 1.0
 * @Date         : 2023-05-14 23:34:46
 * @LastEditTime : 2023-05-16 20:36:54
 */

module dm(Data_in,MemWr,Addr,clk,rst,Data_out);
  	input [31:0]Data_in,Addr;
  	input clk,rst,MemWr;
  	output reg[31:0]Data_out;
  
  	reg  [7:0]DataMem[4095:0]; //4KB
  	wire [11:0]pointer;  //the valid address for 4KB data

  	assign pointer=Addr[11:0]; //4KB data

  	//reset
  	integer i;
  	always@(negedge rst)begin
    		for(i=0;i<4096;i=i+1)
    		DataMem[i]=0;
  	end

  	//store word
  	always@(negedge clk)begin
    		if(MemWr)begin
      			DataMem[pointer]   <= Data_in[31:24]; //32bits->8bits*4
      			DataMem[pointer+1] <= Data_in[23:16];
      			DataMem[pointer+2] <= Data_in[15:8];
      			DataMem[pointer+3] <= Data_in[7:0];
    		end
  	end

    //load word
  	always@(negedge clk)begin
  		if(!MemWr)begin
    			Data_out<={DataMem[pointer],DataMem[pointer+1],DataMem[pointer+2],DataMem[pointer+3]};
  		end
	end

endmodule
    
